-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.1 (lin64) Build 6140274 Wed May 21 22:58:25 MDT 2025
-- Date        : Wed Jun 25 18:12:10 2025
-- Host        : xcoapps73 running 64-bit Red Hat Enterprise Linux release 8.10 (Ootpa)
-- Command     : write_vhdl -force -mode synth_stub
--               /group/bcapps/gpocklas/github/Revision_Control/Check_In_Generated_Outputs/sources/vivado_prj_xci_bd/vivado_prj_xci_bd.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/design_1_axi_noc_0_0_stub.vhdl
-- Design      : design_1_axi_noc_0_0
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xcvc1902-vsva2197-2MP-e-S
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity design_1_axi_noc_0_0 is
  Port ( 
    S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S00_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S00_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S00_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S00_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S00_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S00_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S01_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    S01_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S01_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S01_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S01_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S01_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S01_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    S01_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S01_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S01_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S02_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S02_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S02_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S02_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S02_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S02_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S02_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S02_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    S02_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S02_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S02_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S02_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S02_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S02_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S02_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S02_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S02_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S02_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S02_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    S02_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S02_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S02_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S03_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S03_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S03_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S03_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S03_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S03_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S03_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S03_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    S03_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S03_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S03_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S03_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S03_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S03_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S03_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S03_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S03_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S03_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S03_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    S03_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S03_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S03_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S04_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S04_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S04_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S04_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S04_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S04_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S04_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S04_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    S04_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S04_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S04_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S04_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S04_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S04_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S04_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S04_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S04_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S04_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S04_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    S04_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S04_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S05_AXI_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S05_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S05_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S05_AXI_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S05_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S05_AXI_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S05_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S05_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_wdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    S05_AXI_wstrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S05_AXI_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S05_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
    S05_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
    S05_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S05_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
    S05_AXI_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S05_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    S05_AXI_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S05_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
    S05_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_rdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    S05_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    S05_AXI_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    S05_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M00_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    M00_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M00_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M00_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M01_AXI_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M01_AXI_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
    M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
    M01_AXI_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
    M01_AXI_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M01_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M01_AXI_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
    M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
    M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
    aclk0 : in STD_LOGIC;
    aclk1 : in STD_LOGIC;
    aclk2 : in STD_LOGIC;
    aclk3 : in STD_LOGIC;
    aclk4 : in STD_LOGIC;
    aclk5 : in STD_LOGIC;
    aclk6 : in STD_LOGIC;
    aclk7 : in STD_LOGIC;
    sys_clk0_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk0_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
    CH0_DDR4_0_dqs_t : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CH0_DDR4_0_dqs_c : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CH0_DDR4_0_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
    CH0_DDR4_0_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
    CH0_DDR4_0_bg : out STD_LOGIC_VECTOR ( 1 downto 0 );
    CH0_DDR4_0_act_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_reset_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
    CH0_DDR4_0_dm_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
    CH0_DDR4_0_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
    S04_AXI_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S04_AXI_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S04_AXI_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S04_AXI_awuser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S04_AXI_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S04_AXI_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S04_AXI_ruser : out STD_LOGIC_VECTOR ( 16 downto 0 );
    S04_AXI_wuser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    S03_AXI_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S03_AXI_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S03_AXI_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S03_AXI_awuser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S03_AXI_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S03_AXI_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S03_AXI_ruser : out STD_LOGIC_VECTOR ( 16 downto 0 );
    S03_AXI_wuser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    S02_AXI_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S02_AXI_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S02_AXI_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S02_AXI_awuser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S02_AXI_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S02_AXI_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S02_AXI_ruser : out STD_LOGIC_VECTOR ( 16 downto 0 );
    S02_AXI_wuser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    S00_AXI_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S00_AXI_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S00_AXI_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S00_AXI_awuser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S00_AXI_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S00_AXI_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S00_AXI_ruser : out STD_LOGIC_VECTOR ( 16 downto 0 );
    S00_AXI_wuser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    S05_AXI_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S05_AXI_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S05_AXI_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S05_AXI_awuser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S05_AXI_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S05_AXI_buser : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S05_AXI_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S05_AXI_ruser : out STD_LOGIC_VECTOR ( 16 downto 0 );
    S05_AXI_wuser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    S01_AXI_arid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S01_AXI_aruser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S01_AXI_awid : in STD_LOGIC_VECTOR ( 15 downto 0 );
    S01_AXI_awuser : in STD_LOGIC_VECTOR ( 17 downto 0 );
    S01_AXI_bid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S01_AXI_rid : out STD_LOGIC_VECTOR ( 15 downto 0 );
    S01_AXI_ruser : out STD_LOGIC_VECTOR ( 16 downto 0 );
    S01_AXI_wuser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    M01_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_aruser : out STD_LOGIC_VECTOR ( 17 downto 0 );
    M01_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_awuser : out STD_LOGIC_VECTOR ( 17 downto 0 );
    M01_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M01_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_arid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_aruser : out STD_LOGIC_VECTOR ( 17 downto 0 );
    M00_AXI_awid : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_awuser : out STD_LOGIC_VECTOR ( 17 downto 0 );
    M00_AXI_bid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_rid : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M00_AXI_ruser : in STD_LOGIC_VECTOR ( 16 downto 0 );
    M00_AXI_wuser : out STD_LOGIC_VECTOR ( 16 downto 0 )
  );

  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_axi_noc_0_0 : entity is "design_1_axi_noc_0_0,bd_8be5,{}";
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of design_1_axi_noc_0_0 : entity is "design_1_axi_noc_0_0,bd_8be5,{x_ipProduct=Vivado 2025.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_noc,x_ipVersion=1.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,Component_Name=design_1_axi_noc_0_0,NUM_SI=6,NUM_HBM_BLI=0,BLI_NAMES= ,NUM_MI=2,NUM_NSI=0,NUM_NMI=0,NUM_CLKS=8,SI_DESTID_PINS=,BLI_DESTID_PINS=,SI_SIDEBAND_PINS=,MI_SIDEBAND_PINS=,SECURE_SLR_PMC_TRAFFIC=false,HBM_SIDEBAND_PINS=,SI_USR_INTR_PINS=,MI_USR_INTR_PINS=,MI_INFO_PINS=,SI_NAMES=,MI_NAMES=,NSI_NAMES=,NMI_NAMES=,CLK_NAMES=,NOC_RD_RATE=,NOC_WR_RATE=,NUM_MC=1,NUM_MCP=4,MC_GUI=0,MC_INTERLEAVE_SIZE=128,MC_BOARD_INTRF_EN=true,MC0_FLIPPED_PINOUT=false,MC1_FLIPPED_PINOUT=false,MC2_FLIPPED_PINOUT=false,MC3_FLIPPED_PINOUT=false,MC0_CONFIG_NUM=config17,MC1_CONFIG_NUM=config17,MC2_CONFIG_NUM=config17,MC3_CONFIG_NUM=config17,CH0_DDR4_0_BOARD_INTERFACE=ddr4_dimm1,CH0_DDR4_1_BOARD_INTERFACE=Custom,CH0_DDR4_2_BOARD_INTERFACE=Custom,CH0_DDR4_3_BOARD_INTERFACE=Custom,CH1_DDR4_0_BOARD_INTERFACE=Custom,CH1_DDR4_1_BOARD_INTERFACE=Custom,CH1_DDR4_2_BOARD_INTERFACE=Custom,CH1_DDR4_3_BOARD_INTERFACE=Custom,CH0_LPDDR4_0_BOARD_INTERFACE=Custom,CH0_LPDDR4_1_BOARD_INTERFACE=Custom,CH0_LPDDR4_2_BOARD_INTERFACE=Custom,CH0_LPDDR4_3_BOARD_INTERFACE=Custom,CH1_LPDDR4_0_BOARD_INTERFACE=Custom,CH1_LPDDR4_1_BOARD_INTERFACE=Custom,CH1_LPDDR4_2_BOARD_INTERFACE=Custom,CH1_LPDDR4_3_BOARD_INTERFACE=Custom,sys_clk0_BOARD_INTERFACE=ddr4_dimm1_sma_clk,sys_clk1_BOARD_INTERFACE=Custom,sys_clk2_BOARD_INTERFACE=Custom,sys_clk3_BOARD_INTERFACE=Custom,HBM_NUM_CHNL=0,HBM_START_CHNL=0,HBM_START_PHYSICAL_CHNL=-1,HBM_STACKS=0,HBM_CHNL_PARAM=0,HBM_CTRL_PHY_MODE=Controller_and_Physical_Layer,HBM_NUM_PHY=0,HBM_START_PHY=0,HBM_MEM_BACKDOOR_WRITE=false,HBM_MEM_INIT_MODE=INIT_0,HBM_MEM_INIT_FILE=no_file_loaded,HBM_REF_CLK_SELECTION=Internal,HBM_EXT_REFCLK_IO_STANDARD=NONE,HBM_CHNL_EN_0=false,HBM_CHNL_EN_1=false,HBM_CHNL_EN_2=false,HBM_CHNL_EN_3=false,HBM_CHNL_EN_4=false,HBM_CHNL_EN_5=false,HBM_CHNL_EN_6=false,HBM_CHNL_EN_7=false,HBM_CHNL_EN_8=false,HBM_CHNL_EN_9=false,HBM_CHNL_EN_10=false,HBM_CHNL_EN_11=false,HBM_CHNL_EN_12=false,HBM_CHNL_EN_13=false,HBM_CHNL_EN_14=false,HBM_CHNL_EN_15=false,HBM_AUTO_POPULATE=yes,HBM_MEMORY_FREQ0=1600,HBM_REF_CLK_FREQ0=100.000,HBM_MEMORY_FREQ1=1600,HBM_REF_CLK_FREQ1=100.000,HBM_STACK0_CONFIG= ,HBM_CHNL0_CONFIG=HBM_REF_PERIOD_TEMP_COMP FALSE,HBM_CHNL1_CONFIG= ,HBM_CHNL2_CONFIG= ,HBM_CHNL3_CONFIG= ,HBM_CHNL4_CONFIG= ,HBM_CHNL5_CONFIG= ,HBM_CHNL6_CONFIG= ,HBM_CHNL7_CONFIG= ,HBM_CHNL8_CONFIG= ,HBM_CHNL9_CONFIG= ,HBM_CHNL10_CONFIG= ,HBM_CHNL11_CONFIG= ,HBM_CHNL12_CONFIG= ,HBM_CHNL13_CONFIG= ,HBM_CHNL14_CONFIG= ,HBM_CHNL15_CONFIG= ,HBM_AP_BASE_CONFIG=HBM_CHNL0_CONFIG,HBM_DENSITY_PER_CHNL=NA,HBM_PHY_EN_0=false,HBM_PHY_EN_1=false,HBM_PHY_EN_2=false,HBM_PHY_EN_3=false,HBM_PHY_EN_4=false,HBM_PHY_EN_5=false,HBM_PHY_EN_6=false,HBM_PHY_EN_7=false,HBM_PHY_EN_8=false,HBM_PHY_EN_9=false,HBM_PHY_EN_10=false,HBM_PHY_EN_11=false,HBM_PHY_EN_12=false,HBM_PHY_EN_13=false,HBM_PHY_EN_14=false,HBM_PHY_EN_15=false,HBM_FCV_PARAM=Disable,HBM_MEMORY_MODEL=xilinx_responder,HBM_PHYIO_CNTRL_BLOCK=false,HBM_ST0_EN=false,HBM_ST1_EN=false,HBM_SIMULATION_MODE=BFM,HBM_DFI_CLK_DIV2_EN=false,HBM_HPLL_TEST_PORTS_EN=false,HBM_PHY_DEBUG_PORTS_EN=false,HBM_GBL_REF_RST_EN=false,HBM_VNC_EN=false,HBM_OVERWRITE_PORTCONTROL_REG=false,MC_NAME=MC,LOGO_FILE=data/noc_mc.png,CONTROLLERTYPE=DDR4_SDRAM,USER_NPI_REG_MC_NSU_0_ING=0x01132400,USER_NPI_REG_MC_NSU_0_EGR=0x00134012,USER_NPI_REG_MC_NSU_0_R_EGR=0x01010100,USER_NPI_REG_MC_NSU_0_W_EGR=0x00010100,USER_NPI_REG_MC_NSU_1_ING=0x01132400,USER_NPI_REG_MC_NSU_1_EGR=0x00134012,USER_NPI_REG_MC_NSU_1_R_EGR=0x01010100,USER_NPI_REG_MC_NSU_1_W_EGR=0x00010100,USER_NPI_REG_MC_NSU_2_ING=0x01132400,USER_NPI_REG_MC_NSU_2_EGR=0x00134012,USER_NPI_REG_MC_NSU_2_R_EGR=0x01010100,USER_NPI_REG_MC_NSU_2_W_EGR=0x00010100,USER_NPI_REG_MC_NSU_3_ING=0x01132400,USER_NPI_REG_MC_NSU_3_EGR=0x00134012,USER_NPI_REG_MC_NSU_3_R_EGR=0x01010100,USER_NPI_REG_MC_NSU_3_W_EGR=0x00010100,MC_XPLL_MODE=VarRxVarTx,MC_XPLL_CLKOUT1_PH_CTRL=0x3,MC_XPLL_CLKOUT2_PH_CTRL=0x1,MC_XPLL_DSKW_DLY1=12,MC_XPLL_DSKW_DLY2=15,MC_XPLL_DSKW_DLY_EN1=TRUE,MC_XPLL_DSKW_DLY_EN2=TRUE,MC_XPLL_DSKW_DLY_PATH1=FALSE,MC_XPLL_DSKW_DLY_PATH2=TRUE,MC_XPLL_CLKOUT1_PHASE=0.000,MC_XPLL_CLKOUT1_PERIOD=1250,MC_XPLL_DIV4_CLKOUT12=TRUE,MC_XPLL_DIV4_CLKOUT3=TRUE,MC_XPLL_CLKOUTPHY_CASCIN_EN=TRUE,MC_XPLL_CLKOUTPHY_CASCOUT_EN=FALSE,MC_XPLL_DESKEW_MUXIN_SEL=TRUE,MC_XPLL_DESKEW2_MUXIN_SEL=TRUE,MC_XPLL_CLKOUT2_PHASE=0.0,MC_REG_RD_DRR_TKN_P0=0x00040404,MC_REG_RD_DRR_TKN_P1=0x00040404,MC_REG_RD_DRR_TKN_P2=0x00040404,MC_REG_RD_DRR_TKN_P3=0x00040404,MC_REG_WR_DRR_TKN_P0=0x00000404,MC_REG_WR_DRR_TKN_P1=0x00000404,MC_REG_WR_DRR_TKN_P2=0x00000404,MC_REG_WR_DRR_TKN_P3=0x00000404,MC_REG_QOS0=0x000F00F0,MC_REG_QOS1=0x00200804,MC_REG_QOS2=0x00000802,MC_REG_QOS_TIMEOUT0=0x01084210,MC_REG_QOS_TIMEOUT1=0xFFFFFFFF,MC_REG_QOS_TIMEOUT2=0x000000FF,MC_REG_RATE_CTRL_SCALE=0x00000000,MC_REG_P0_LLR_RATE_CTRL=0x003FFC0F,MC_REG_P0_ISR_RATE_CTRL=0x003FFC0F,MC_REG_P0_BER_RATE_CTRL=0x003FFC0F,MC_REG_P0_ISW_RATE_CTRL=0x003FFC0F,MC_REG_P0_BEW_RATE_CTRL=0x003FFC0F,MC_REG_P1_LLR_RATE_CTRL=0x003FFC0F,MC_REG_P1_ISR_RATE_CTRL=0x003FFC0F,MC_REG_P1_BER_RATE_CTRL=0x003FFC0F,MC_REG_P1_ISW_RATE_CTRL=0x003FFC0F,MC_REG_P1_BEW_RATE_CTRL=0x003FFC0F,MC_REG_P2_LLR_RATE_CTRL=0x003FFC0F,MC_REG_P2_ISR_RATE_CTRL=0x003FFC0F,MC_REG_P2_BER_RATE_CTRL=0x003FFC0F,MC_REG_P2_ISW_RATE_CTRL=0x003FFC0F,MC_REG_P2_BEW_RATE_CTRL=0x003FFC0F,MC_REG_P3_LLR_RATE_CTRL=0x003FFC0F,MC_REG_P3_ISR_RATE_CTRL=0x003FFC0F,MC_REG_P3_BER_RATE_CTRL=0x003FFC0F,MC_REG_P3_ISW_RATE_CTRL=0x003FFC0F,MC_REG_P3_BEW_RATE_CTRL=0x003FFC0F,MC_REG_CMDQ_CTRL0=0x01084210,MC_REG_CMDQ_CTRL1=0x01084210,MC_REG_CMDQ_LLR_RATE_CTRL=0x003FFC0F,MC_REG_CMDQ_ISR_RATE_CTRL=0x003FFC0F,MC_REG_CMDQ_BER_RATE_CTRL=0x003FFC0F,MC_REG_CMDQ_ISW_RATE_CTRL=0x003FFC0F,MC_REG_CMDQ_BEW_RATE_CTRL=0x003FFC0F,MC_REG_QOS_RATE_CTRL_SCALE=0x00000000,MC_DC_CMD_CREDITS=0x000002A8,MC_EXMON_CLR_EXE=0x00000100,MC_XMPU_CTRL=0x0000000B,MC_XMPU_START_LO0=0x00000000,MC_XMPU_START_HI0=0x00000000,MC_XMPU_END_LO0=0x00000000,MC_XMPU_END_HI0=0x00000000,MC_XMPU_MASTER0=0x00000000,MC_XMPU_CONFIG0=0x00000008,MC_XMPU_START_LO1=0x00000000,MC_XMPU_START_HI1=0x00000000,MC_XMPU_END_LO1=0x00000000,MC_XMPU_END_HI1=0x00000000,MC_XMPU_MASTER1=0x00000000,MC_XMPU_CONFIG1=0x00000008,MC_XMPU_START_LO2=0x00000000,MC_XMPU_START_HI2=0x00000000,MC_XMPU_END_LO2=0x00000000,MC_XMPU_END_HI2=0x00000000,MC_XMPU_MASTER2=0x00000000,MC_XMPU_CONFIG2=0x00000008,MC_XMPU_START_LO3=0x00000000,MC_XMPU_START_HI3=0x00000000,MC_XMPU_END_LO3=0x00000000,MC_XMPU_END_HI3=0x00000000,MC_XMPU_MASTER3=0x00000000,MC_XMPU_CONFIG3=0x00000008,MC_XMPU_START_LO4=0x00000000,MC_XMPU_START_HI4=0x00000000,MC_XMPU_END_LO4=0x00000000,MC_XMPU_END_HI4=0x00000000,MC_XMPU_MASTER4=0x00000000,MC_XMPU_CONFIG4=0x00000008,MC_XMPU_START_LO5=0x00000000,MC_XMPU_START_HI5=0x00000000,MC_XMPU_END_LO5=0x00000000,MC_XMPU_END_HI5=0x00000000,MC_XMPU_MASTER5=0x00000000,MC_XMPU_CONFIG5=0x00000008,MC_XMPU_START_LO6=0x00000000,MC_XMPU_START_HI6=0x00000000,MC_XMPU_END_LO6=0x00000000,MC_XMPU_END_HI6=0x00000000,MC_XMPU_MASTER6=0x00000000,MC_XMPU_CONFIG6=0x00000008,MC_XMPU_START_LO7=0x00000000,MC_XMPU_START_HI7=0x00000000,MC_XMPU_END_LO7=0x00000000,MC_XMPU_END_HI7=0x00000000,MC_XMPU_MASTER7=0x00000000,MC_XMPU_CONFIG7=0x00000008,MC_XMPU_START_LO8=0x00000000,MC_XMPU_START_HI8=0x00000000,MC_XMPU_END_LO8=0x00000000,MC_XMPU_END_HI8=0x00000000,MC_XMPU_MASTER8=0x00000000,MC_XMPU_CONFIG8=0x00000008,MC_XMPU_START_LO9=0x00000000,MC_XMPU_START_HI9=0x00000000,MC_XMPU_END_LO9=0x00000000,MC_XMPU_END_HI9=0x00000000,MC_XMPU_MASTER9=0x00000000,MC_XMPU_CONFIG9=0x00000008,MC_XMPU_START_LO10=0x00000000,MC_XMPU_START_HI10=0x00000000,MC_XMPU_END_LO10=0x00000000,MC_XMPU_END_HI10=0x00000000,MC_XMPU_MASTER10=0x00000000,MC_XMPU_CONFIG10=0x00000008,MC_XMPU_START_LO11=0x00000000,MC_XMPU_START_HI11=0x00000000,MC_XMPU_END_LO11=0x00000000,MC_XMPU_END_HI11=0x00000000,MC_XMPU_MASTER11=0x00000000,MC_XMPU_CONFIG11=0x00000008,MC_XMPU_START_LO12=0x00000000,MC_XMPU_START_HI12=0x00000000,MC_XMPU_END_LO12=0x00000000,MC_XMPU_END_HI12=0x00000000,MC_XMPU_MASTER12=0x00000000,MC_XMPU_CONFIG12=0x00000008,MC_XMPU_START_LO13=0x00000000,MC_XMPU_START_HI13=0x00000000,MC_XMPU_END_LO13=0x00000000,MC_XMPU_END_HI13=0x00000000,MC_XMPU_MASTER13=0x00000000,MC_XMPU_CONFIG13=0x00000008,MC_XMPU_START_LO14=0x00000000,MC_XMPU_START_HI14=0x00000000,MC_XMPU_END_LO14=0x00000000,MC_XMPU_END_HI14=0x00000000,MC_XMPU_MASTER14=0x00000000,MC_XMPU_CONFIG14=0x00000008,MC_XMPU_START_LO15=0x00000000,MC_XMPU_START_HI15=0x00000000,MC_XMPU_END_LO15=0x00000000,MC_XMPU_END_HI15=0x00000000,MC_XMPU_MASTER15=0x00000000,MC_XMPU_CONFIG15=0x00000008,MC_REG_ADEC0=0x00000000,MC_REG_ADEC1=0x00000000,MC_REG_ADEC2=0x00005000,MC_REG_ADEC3=0x00005000,MC_REG_ADEC4=0x279A5923,MC_REG_ADEC5=0x1349140F,MC_REG_ADEC6=0x185D6554,MC_REG_ADEC7=0x1D71B699,MC_REG_ADEC8=0x030207DE,MC_REG_ADEC9=0x081C6144,MC_REG_ADEC10=0x0D30B289,MC_REG_ADEC11=0x001A284E,MC_REG_NSU0_PORT=0x00000000,MC_REG_NSU1_PORT=0x00000000,MC_REG_NSU2_PORT=0x00000000,MC_REG_NSU3_PORT=0x00000000,MC_UB_CLK_MUX=0x00000000,MC_TCK=628,MC_MEMORY_TIMEPERIOD0=625,MC_MEMORY_TIMEPERIOD1=625,MC_OP_TIMEPERIOD0=625,MC_IP_TIMEPERIOD0_FOR_OP=1250,MC_FREQ_SEL=SYS_CLK_FROM_MEMORY_CLK,MC_MEMORY_FREQUENCY1=625,MC_MEMORY_FREQUENCY2=625,MC_INPUT_FREQUENCY0=200.000,MC_INPUTCLK0_PERIOD=5000,MC_INPUT_FREQUENCY1=400.000,MC_INPUTCLK1_PERIOD=2500,MC_SYSTEM_CLOCK=Differential,MC_INTERNAL_SYSCLK_EN=false,MC_MEMORY_DEVICETYPE=UDIMMs,MC_MEMORY_SPEEDGRADE=DDR4-3200AA(22-22-22),MC_COMPONENT_WIDTH=x8,MC_MEM_DEVICE_WIDTH=x8,MC_MAIN_MODULE_NAME=DDRMC_MAIN_0,MC_NOC_MODULE_NAME=DDRMC_NOC_0,MC_MAIN_BASE_ADDR=0xF6150000,MC_NOC_BASE_ADDR=0xF6070000,MC_COMPONENT_DENSITY=8Gb,MC_MEMORY_DENSITY=8GB,MC_MEMORY_DEVICE_DENSITY=8Gb,MC_TCKEMIN=8,MC_TCKE=8,MC_TDQSCK_MIN=1500,MC_TDQSCK_MAX=0,MC_TDQSS_MIN=0.75,MC_TDQSS_MAX=1.25,MC_TDQS2DQ_MIN=0,MC_TDQS2DQ_MAX=0,MC_TFAW=21000,MC_TFAW_nCK=34,MC_TFAW_DLR=0,MC_TMRD=8,MC_TMRD_div4=0,MC_TMRD_nCK=0,MC_TCMR_MRD=0,MC_TRPRE=0.9,MC_TSTAB=0,MC_INTERNAL_CA_PARITY_EN=FALSE,MC_PARITY=false,MC_PARITYLATENCY=0,MC_REGVAL_COMPARE=false,MC_F1_PARITYLATENCY=0,MC_TPAR_ALERT_ON=10,MC_F1_TPAR_ALERT_ON=0,MC_TPAR_ALERT_PW_MAX=192,MC_F1_TPAR_ALERT_PW_MAX=0,MC_TPDM_RD=0,MC_F1_TPDM_RD=0,MC_RCD_PARITY=false,MC_TRAS=32000,MC_TRAS_nCK=0,MC_TRCD=13750,MC_TRCD_nCK=0,MC_F1_TRCD_nCK=0,MC_TREFI=7800000,MC_TRFC=350000,MC_TRP=13750,MC_SILICON_REVISION=NA,MC_TOSCO=0,MC_TOSCO_nCK=0,MC_TRPST=0.4,MC_TWPRE=0.9,MC_TWPST=0.33,MC_TRRD_S=4,MC_TRRD_S_nCK=1,MC_TRRD_L=8,MC_TRRD_L_nCK=1,MC_TRRD_DLR=0,MC_TRTP=7500,MC_TRTP_nCK=12,MC_TMOD=24,MC_TMOD_nCK=24,MC_TMPRR=1,MC_TBCW=0,MC_TMRC=0,MC_TWR=15000,MC_TWR_nCK=0,MC_TWTR_S=2500,MC_TWTR_L=7500,MC_TXPR=576,MC_TXPR_nCK=5,MC_TXPMIN=10,MC_TXP=10,MC_TZQCS=128,MC_TZQCS_ITVL=1000000000,MC_TZQ_START_ITVL=0,MC_TZQINIT=1024,MC_TZQLAT=0,MC_TZQLAT_div4=0,MC_TZQLAT_nCK=0,MC_TMRW=0,MC_TMRW_div4=0,MC_TMRW_nCK=0,MC_TMRR=8,MC_TCCD_3DS=0,MC_TRTW=350,MC_TREFIPB=0,MC_TRFCAB=0,MC_TRFCPB=0,MC_TPBR2PBR=0,MC_TRPAB=0,MC_TRPAB_nCK=0,MC_TRPPB=0,MC_TRPPB_nCK=0,MC_TRRD=0,MC_TRRD_nCK=0,MC_TWTR=0,MC_TWTR_nCK=0,MC_TCCD=0,MC_TCCDMW=32,MC_ZQINTVL=350,MC_RTT=RZQ/6,MC_CLAMSHELL=false,MC_NO_CHANNELS=Single,MC_DATAWIDTH=64,MC_ROWADDRESSWIDTH=16,MC_COLUMNADDRESSWIDTH=10,MC_BG_WIDTH=2,MC_BA_WIDTH=2,MC_CA_MIRROR=false,MC_RANK=1,MC_STACKHEIGHT=1,MC_SLOT=Single,MC_ECC=false,MC_DDR4_2T=Disable,MC_CHANNEL_INTERLEAVING=false,MC_CH_INTERLEAVING_SIZE=NONE,MC_CASLATENCY=22,MC_CASWRITELATENCY=16,MC_ORDERING=Strict,MC_ADDRESSMAP=ROW_COLUMN_BANK,MC_SELFREFRESH=false,MC_SAVERESTORE=false,MC_SIMMODE=BFM,MC_POWERMODES=true,MC_ZQCS_FREQUENCY=true,MC_USERREFRESH=false,MC_LPDDR4_REFRESH_TYPE=ALL_BANK,MC_ADD_CMD_DELAY_EN=Disable,MC_ADD_CMD_DELAY=0,MC_F1_ADD_CMD_DELAY_EN=Disable,MC_F1_ADD_CMD_DELAY=0,MC_ZQCS_PIN=true,MC_SCRUBBING=off,MC_SVFLOW=Disable,MC_SKIPCAL=Disable,MC_FCV_FULLCAL=Disable,MC_PRUNECHIP_SIM_CHANGES=Disable,MC_MEM_ADDRESS_MAP=ROW_COLUMN_BANK,MC_TCCD_S=4,MC_TCCD_L=8,MC_TCCD_L_nCK=5,MC_TRC=45750,MC_REFRESH_RATE=1x,MC_REFRESH_SPEED=1x_SPEED-NORMAL_TEMPERATURE,MC_TRFC_DLR=0,MC_CORRECT_EN=1,MC_CLA=0,MC_F1_CLA=0,MC_RCD_DELAY=0,MC_F1_RCD_DELAY=0,MC_REGION=0,MC_EN_NPP_MONITOR=1,MC_DISABLE_DATA_CHECK=1,MC_LR_WIDTH=1,MC_CS_WIDTH=1,MC_PRE_DEF_ADDR_MAP_SEL=ROW_BANK_COLUMN_BGO,MC_USER_DEFINED_ADDRESS_MAP=16RA-2BA-2BG-10CA,MC_ADDR_BIT43=NA,MC_ADDR_BIT42=NA,MC_ADDR_BIT41=NA,MC_ADDR_BIT40=NA,MC_ADDR_BIT39=NA,MC_ADDR_BIT38=NA,MC_ADDR_BIT37=NA,MC_ADDR_BIT36=NA,MC_ADDR_BIT35=NA,MC_ADDR_BIT34=NA,MC_ADDR_BIT33=NA,MC_ADDR_BIT32=RA15,MC_ADDR_BIT31=RA14,MC_ADDR_BIT30=RA13,MC_ADDR_BIT29=RA12,MC_ADDR_BIT28=RA11,MC_ADDR_BIT27=RA10,MC_ADDR_BIT26=RA9,MC_ADDR_BIT25=RA8,MC_ADDR_BIT24=RA7,MC_ADDR_BIT23=RA6,MC_ADDR_BIT22=RA5,MC_ADDR_BIT21=RA4,MC_ADDR_BIT20=RA3,MC_ADDR_BIT19=RA2,MC_ADDR_BIT18=RA1,MC_ADDR_BIT17=RA0,MC_ADDR_BIT16=BA1,MC_ADDR_BIT15=BA0,MC_ADDR_BIT14=BG1,MC_ADDR_BIT13=CA9,MC_ADDR_BIT12=CA8,MC_ADDR_BIT11=CA7,MC_ADDR_BIT10=CA6,MC_ADDR_BIT9=CA5,MC_ADDR_BIT8=CA4,MC_ADDR_BIT7=CA3,MC_ADDR_BIT6=BG0,MC_ADDR_BIT5=CA2,MC_ADDR_BIT4=CA1,MC_ADDR_BIT3=CA0,MC_ADDR_BIT2=NC,MC_ADDR_BIT1=NC,MC_ADDR_BIT0=NC,MC_CHAN_REGION0=DDR_LOW0,MC_CHAN_REGION1=NONE,MC_DQ_WIDTH=64,MC_DQS_WIDTH=8,MC_DM_WIDTH=8,MC_CK_WIDTH=1,MC_CKE_WIDTH=1,MC_ADDR_WIDTH=17,MC_BURST_LENGTH=8,MC_ODT_WIDTH=1,MC_NUM_CK=1,MC_LP4_PIN_EFFICIENT=false,MC_CH0_LP4_CHA_ENABLE=false,MC_CH0_LP4_CHB_ENABLE=false,MC_CH1_LP4_CHA_ENABLE=false,MC_CH1_LP4_CHB_ENABLE=false,MC_LP4_DQ_A_WIDTH=0,MC_LP4_DQ_B_WIDTH=0,MC_LP4_DQS_A_WIDTH=0,MC_LP4_DQS_B_WIDTH=0,MC_LP4_DMI_A_WIDTH=0,MC_LP4_DMI_B_WIDTH=0,MC_LP4_CA_A_WIDTH=0,MC_LP4_CA_B_WIDTH=0,MC_LP4_CKT_A_WIDTH=0,MC_LP4_CKT_B_WIDTH=0,MC_LP4_CKE_A_WIDTH=0,MC_LP4_CKE_B_WIDTH=0,MC_LP4_CS_A_WIDTH=0,MC_LP4_CS_B_WIDTH=0,MC_LP4_RESETN_WIDTH=0,MC_TEMP_DIR_DELETE=TRUE,MC_TFAWMIN=21000,MC_TMRDMIN=8,MC_TRASMIN=32000,MC_TRCDMIN=13750,MC_TRPMIN=13750,MC_TRCMIN=45750,MC_TRRD_S_MIN=4,MC_TRRD_L_MIN=8,MC_TRTPMIN=7500,MC_TOSCOMIN=0,MC_TWRMIN=15000,MC_TWTRMIN=0,MC_TWTR_S_MIN=2500,MC_TWTR_L_MIN=0,MC_TRFCMIN=350000,MC_TCCD_L_MIN=8,MC_TCCD_3DS_MIN=0,MC_TMOD_MIN=24,MC_TRPABMIN=0,MC_TRPPBMIN=0,MC_TRRDMIN=0,MC_TZQCAL=0,MC_TZQCAL_div4=0,MC_TZQLATMIN=0,MC_TMRWMIN=0,MC_TRFCABMIN=0,MC_TRFCPBMIN=0,MC_TPBR2PBRMIN=0,MC_EN_ECC_SCRUBBING=false,MC_EN_BACKGROUND_SCRUBBING=false,MC_ECC_SCRUB_PERIOD=0x003E80,MC_PER_RD_INTVL=20000000,MC_INIT_MEM_USING_ECC_SCRUB=false,MC_IDLE_TIME_ENTR_PWR_DOWN_MODE=0x00000AA,MC_IDLE_TIME_ENTR_SELF_REF_MODE=0x0020000,MC_WRITE_DM_DBI=DM_NO_DBI,MC_READ_DBI=false,MC_ATTR_FILE=sidefile.xdc,MC_EN_INTR_RESP=TRUE,MC_EXTENDED_WDQS=TRUE,MC_ODTLon=0,MC_F1_ODTLon=0,MC_TODTon_MIN=0,MC_F1_TODTon_MIN=0,MC_LP4_OPERATING_TEMP=STANDARD,MC_CONFIG_NUM=config17,MC_FREQ_SWITCHING_EN=FALSE,MC_FREQ_PARAM=F0,MC_IP_TIMEPERIOD1=625,MC_OP_TIMEPERIOD1=625,MC_F1_CASLATENCY=24,MC_F1_CASWRITELATENCY=20,MC_F1_TFAW=21000,MC_F1_TFAWMIN=21000,MC_F1_TFAW_nCK=0,MC_F1_TRRD_S=4,MC_F1_TRRD_S_MIN=4,MC_F1_TRRD_L=8,MC_F1_TRRD_L_MIN=8,MC_F1_TRTP=7500,MC_F1_TRTPMIN=7500,MC_F1_TRTP_nCK=0,MC_F1_TWTR_S=2500,MC_F1_TWTR_S_MIN=2500,MC_F1_TWTR_L=7500,MC_F1_TWTR_L_MIN=7500,MC_F1_TCCD_L=8,MC_F1_TCCD_L_MIN=8,MC_F1_TCCD_3DS=0,MC_F1_TCCD_3DS_MIN=0,MC_F1_TMOD=24,MC_F1_TMOD_MIN=24,MC_F1_TCKEMIN=0,MC_F1_TCKE=0,MC_F1_TXPMIN=0,MC_F1_TXP=0,MC_F1_TMRD=8,MC_F1_TMRD_nCK=0,MC_F1_TMRDMIN=8,MC_F1_TRAS=32000,MC_F1_TRAS_nCK=0,MC_F1_TRASMIN=32000,MC_F1_TRCD=13750,MC_F1_TRCDMIN=13750,MC_F1_TRPAB=0,MC_F1_TRPAB_nCK=0,MC_F1_TRPABMIN=0,MC_F1_TRPPB=0,MC_F1_TRPPB_nCK=0,MC_F1_TRPPBMIN=0,MC_F1_TRRD=0,MC_F1_TRRDMIN=0,MC_F1_TRRD_nCK=0,MC_F1_TWR=15000,MC_F1_TWR_nCK=0,MC_F1_TWRMIN=15000,MC_F1_TWTR=0,MC_F1_TWTR_nCK=0,MC_F1_TWTRMIN=0,MC_F1_TZQLAT=0,MC_F1_TZQLAT_nCK=0,MC_F1_TZQLATMIN=0,MC_F1_TMRW=0,MC_F1_TMRWMIN=0,MC_F1_TOSCO=0,MC_F1_TOSCO_nCK=0,MC_F1_TOSCOMIN=0,MC_F1_LPDDR4_MR1=0x0000,MC_F1_LPDDR4_MR2=0x0000,MC_F1_LPDDR4_MR3=0x0000,MC_F1_LPDDR4_MR11=0x0000,MC_F1_LPDDR4_MR13=0x0000,MC_F1_LPDDR4_MR22=0x0000,MC_UBLAZE_APB_INTF=FALSE,MC_REF_AND_PER_CAL_INTF=FALSE,MC_DDR4_CTLE=000,MC_READ_BANDWIDTH=6400.000,MC_WRITE_BANDWIDTH=6400.000,MC_ECC_SCRUB_SIZE=8192,MC_OTF_SCRUBBING=false,MC_IBUFDISABLE=false,MC_DDR_INIT_TIMEOUT=0x00079C3E,MC_EN_PERF_STATS=false,MC_XLNX_RESPONDER=true,MC_VNC_ENABLE=FALSE,MC_DEVICE_TYPE=S80,MC_NETLIST_SIMULATION=false,MC_DDR4_MIGRATION=false,MC_CH0_DDR4_CK_SKEW_0=0,MC_CH0_DDR4_CK_SKEW_1=0,MC_CH0_DDR4_CK_SKEW_2=0,MC_CH0_DDR4_CK_SKEW_3=0,MC_CH0_DDR4_ADDR_SKEW_0=0,MC_CH0_DDR4_ADDR_SKEW_1=0,MC_CH0_DDR4_ADDR_SKEW_2=0,MC_CH0_DDR4_ADDR_SKEW_3=0,MC_CH0_DDR4_ADDR_SKEW_4=0,MC_CH0_DDR4_ADDR_SKEW_5=0,MC_CH0_DDR4_ADDR_SKEW_6=0,MC_CH0_DDR4_ADDR_SKEW_7=0,MC_CH0_DDR4_ADDR_SKEW_8=0,MC_CH0_DDR4_ADDR_SKEW_9=0,MC_CH0_DDR4_ADDR_SKEW_10=0,MC_CH0_DDR4_ADDR_SKEW_11=0,MC_CH0_DDR4_ADDR_SKEW_12=0,MC_CH0_DDR4_ADDR_SKEW_13=0,MC_CH0_DDR4_ADDR_SKEW_14=0,MC_CH0_DDR4_ADDR_SKEW_15=0,MC_CH0_DDR4_ADDR_SKEW_16=0,MC_CH0_DDR4_ADDR_SKEW_17=0,MC_CH0_DDR4_BA_SKEW_0=0,MC_CH0_DDR4_BA_SKEW_1=0,MC_CH0_DDR4_BG_SKEW_0=0,MC_CH0_DDR4_BG_SKEW_1=0,MC_CH0_DDR4_CS_SKEW_0=0,MC_CH0_DDR4_CS_SKEW_1=0,MC_CH0_DDR4_CS_SKEW_2=0,MC_CH0_DDR4_CS_SKEW_3=0,MC_CH0_DDR4_CKE_SKEW_0=0,MC_CH0_DDR4_CKE_SKEW_1=0,MC_CH0_DDR4_CKE_SKEW_2=0,MC_CH0_DDR4_CKE_SKEW_3=0,MC_CH0_DDR4_ACT_SKEW=0,MC_CH0_DDR4_PAR_SKEW=0,MC_CH0_DDR4_ODT_SKEW_0=0,MC_CH0_DDR4_ODT_SKEW_1=0,MC_CH0_DDR4_ODT_SKEW_2=0,MC_CH0_DDR4_ODT_SKEW_3=0,MC_CH0_DDR4_LR_SKEW_0=0,MC_CH0_DDR4_LR_SKEW_1=0,MC_CH0_DDR4_LR_SKEW_2=0,MC_CH1_DDR4_CK_SKEW_0=0,MC_CH1_DDR4_CK_SKEW_1=0,MC_CH1_DDR4_CK_SKEW_2=0,MC_CH1_DDR4_CK_SKEW_3=0,MC_CH1_DDR4_ADDR_SKEW_0=0,MC_CH1_DDR4_ADDR_SKEW_1=0,MC_CH1_DDR4_ADDR_SKEW_2=0,MC_CH1_DDR4_ADDR_SKEW_3=0,MC_CH1_DDR4_ADDR_SKEW_4=0,MC_CH1_DDR4_ADDR_SKEW_5=0,MC_CH1_DDR4_ADDR_SKEW_6=0,MC_CH1_DDR4_ADDR_SKEW_7=0,MC_CH1_DDR4_ADDR_SKEW_8=0,MC_CH1_DDR4_ADDR_SKEW_9=0,MC_CH1_DDR4_ADDR_SKEW_10=0,MC_CH1_DDR4_ADDR_SKEW_11=0,MC_CH1_DDR4_ADDR_SKEW_12=0,MC_CH1_DDR4_ADDR_SKEW_13=0,MC_CH1_DDR4_ADDR_SKEW_14=0,MC_CH1_DDR4_ADDR_SKEW_15=0,MC_CH1_DDR4_ADDR_SKEW_16=0,MC_CH1_DDR4_ADDR_SKEW_17=0,MC_CH1_DDR4_BA_SKEW_0=0,MC_CH1_DDR4_BA_SKEW_1=0,MC_CH1_DDR4_BG_SKEW_0=0,MC_CH1_DDR4_BG_SKEW_1=0,MC_CH1_DDR4_CS_SKEW_0=0,MC_CH1_DDR4_CS_SKEW_1=0,MC_CH1_DDR4_CS_SKEW_2=0,MC_CH1_DDR4_CS_SKEW_3=0,MC_CH1_DDR4_CKE_SKEW_0=0,MC_CH1_DDR4_CKE_SKEW_1=0,MC_CH1_DDR4_CKE_SKEW_2=0,MC_CH1_DDR4_CKE_SKEW_3=0,MC_CH1_DDR4_ACT_SKEW=0,MC_CH1_DDR4_PAR_SKEW=0,MC_CH1_DDR4_ODT_SKEW_0=0,MC_CH1_DDR4_ODT_SKEW_1=0,MC_CH1_DDR4_ODT_SKEW_2=0,MC_CH1_DDR4_ODT_SKEW_3=0,MC_CH1_DDR4_LR_SKEW_0=0,MC_CH1_DDR4_LR_SKEW_1=0,MC_CH1_DDR4_LR_SKEW_2=0,MC_LP4_OVERWRITE_IO_PROP=false,MC_MIN_VLD_CNT_CTRL=false,MC_OFFSET_ADDR_FOR_INTLV=None,MC_SHARED_SEGMENTS=0,MC_CAL_MASK_POLL=ENABLE,MC_CH0_LP4_CK_A_SKEW_0=0,MC_CH0_LP4_CK_A_SKEW_1=0,MC_CH0_LP4_CK_A_SKEW_2=0,MC_CH0_LP4_CK_A_SKEW_3=0,MC_CH0_LP4_CK_B_SKEW_0=0,MC_CH0_LP4_CK_B_SKEW_1=0,MC_CH0_LP4_CK_B_SKEW_2=0,MC_CH0_LP4_CK_B_SKEW_3=0,MC_CH0_LP4_CKE_A_SKEW_0=0,MC_CH0_LP4_CKE_A_SKEW_1=0,MC_CH0_LP4_CKE_A_SKEW_2=0,MC_CH0_LP4_CKE_A_SKEW_3=0,MC_CH0_LP4_CKE_B_SKEW_0=0,MC_CH0_LP4_CKE_B_SKEW_1=0,MC_CH0_LP4_CKE_B_SKEW_2=0,MC_CH0_LP4_CKE_B_SKEW_3=0,MC_CH0_LP4_CS_A_SKEW_0=0,MC_CH0_LP4_CS_A_SKEW_1=0,MC_CH0_LP4_CS_A_SKEW_2=0,MC_CH0_LP4_CS_A_SKEW_3=0,MC_CH0_LP4_CS_B_SKEW_0=0,MC_CH0_LP4_CS_B_SKEW_1=0,MC_CH0_LP4_CS_B_SKEW_2=0,MC_CH0_LP4_CS_B_SKEW_3=0,MC_CH1_LP4_CK_A_SKEW_0=0,MC_CH1_LP4_CK_A_SKEW_1=0,MC_CH1_LP4_CK_A_SKEW_2=0,MC_CH1_LP4_CK_A_SKEW_3=0,MC_CH1_LP4_CK_B_SKEW_0=0,MC_CH1_LP4_CK_B_SKEW_1=0,MC_CH1_LP4_CK_B_SKEW_2=0,MC_CH1_LP4_CK_B_SKEW_3=0,MC_CH1_LP4_CKE_A_SKEW_0=0,MC_CH1_LP4_CKE_A_SKEW_1=0,MC_CH1_LP4_CKE_A_SKEW_2=0,MC_CH1_LP4_CKE_A_SKEW_3=0,MC_CH1_LP4_CKE_B_SKEW_0=0,MC_CH1_LP4_CKE_B_SKEW_1=0,MC_CH1_LP4_CKE_B_SKEW_2=0,MC_CH1_LP4_CKE_B_SKEW_3=0,MC_CH1_LP4_CS_A_SKEW_0=0,MC_CH1_LP4_CS_A_SKEW_1=0,MC_CH1_LP4_CS_A_SKEW_2=0,MC_CH1_LP4_CS_A_SKEW_3=0,MC_CH1_LP4_CS_B_SKEW_0=0,MC_CH1_LP4_CS_B_SKEW_1=0,MC_CH1_LP4_CS_B_SKEW_2=0,MC_CH1_LP4_CS_B_SKEW_3=0,MC_ISOC_READ_TIMEOUT=3,MC_ISOC_WRITE_TIMEOUT=3,MC_PIN_LOC=None,IS_DANGLING_NSU=0}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of design_1_axi_noc_0_0 : entity is "yes";
end design_1_axi_noc_0_0;

architecture stub of design_1_axi_noc_0_0 is
  attribute syn_black_box : boolean;
  attribute black_box_pad_pin : string;
  attribute syn_black_box of stub : architecture is true;
  attribute black_box_pad_pin of stub : architecture is "S00_AXI_awaddr[63:0],S00_AXI_awlen[7:0],S00_AXI_awsize[2:0],S00_AXI_awburst[1:0],S00_AXI_awlock[0:0],S00_AXI_awcache[3:0],S00_AXI_awprot[2:0],S00_AXI_awregion[3:0],S00_AXI_awqos[3:0],S00_AXI_awvalid[0:0],S00_AXI_awready[0:0],S00_AXI_wdata[127:0],S00_AXI_wstrb[15:0],S00_AXI_wlast[0:0],S00_AXI_wvalid[0:0],S00_AXI_wready[0:0],S00_AXI_bresp[1:0],S00_AXI_bvalid[0:0],S00_AXI_bready[0:0],S00_AXI_araddr[63:0],S00_AXI_arlen[7:0],S00_AXI_arsize[2:0],S00_AXI_arburst[1:0],S00_AXI_arlock[0:0],S00_AXI_arcache[3:0],S00_AXI_arprot[2:0],S00_AXI_arregion[3:0],S00_AXI_arqos[3:0],S00_AXI_arvalid[0:0],S00_AXI_arready[0:0],S00_AXI_rdata[127:0],S00_AXI_rresp[1:0],S00_AXI_rlast[0:0],S00_AXI_rvalid[0:0],S00_AXI_rready[0:0],S01_AXI_awaddr[63:0],S01_AXI_awlen[7:0],S01_AXI_awsize[2:0],S01_AXI_awburst[1:0],S01_AXI_awlock[0:0],S01_AXI_awcache[3:0],S01_AXI_awprot[2:0],S01_AXI_awregion[3:0],S01_AXI_awqos[3:0],S01_AXI_awvalid[0:0],S01_AXI_awready[0:0],S01_AXI_wdata[127:0],S01_AXI_wstrb[15:0],S01_AXI_wlast[0:0],S01_AXI_wvalid[0:0],S01_AXI_wready[0:0],S01_AXI_bresp[1:0],S01_AXI_bvalid[0:0],S01_AXI_bready[0:0],S01_AXI_araddr[63:0],S01_AXI_arlen[7:0],S01_AXI_arsize[2:0],S01_AXI_arburst[1:0],S01_AXI_arlock[0:0],S01_AXI_arcache[3:0],S01_AXI_arprot[2:0],S01_AXI_arregion[3:0],S01_AXI_arqos[3:0],S01_AXI_arvalid[0:0],S01_AXI_arready[0:0],S01_AXI_rdata[127:0],S01_AXI_rresp[1:0],S01_AXI_rlast[0:0],S01_AXI_rvalid[0:0],S01_AXI_rready[0:0],S02_AXI_awaddr[63:0],S02_AXI_awlen[7:0],S02_AXI_awsize[2:0],S02_AXI_awburst[1:0],S02_AXI_awlock[0:0],S02_AXI_awcache[3:0],S02_AXI_awprot[2:0],S02_AXI_awregion[3:0],S02_AXI_awqos[3:0],S02_AXI_awvalid[0:0],S02_AXI_awready[0:0],S02_AXI_wdata[127:0],S02_AXI_wstrb[15:0],S02_AXI_wlast[0:0],S02_AXI_wvalid[0:0],S02_AXI_wready[0:0],S02_AXI_bresp[1:0],S02_AXI_bvalid[0:0],S02_AXI_bready[0:0],S02_AXI_araddr[63:0],S02_AXI_arlen[7:0],S02_AXI_arsize[2:0],S02_AXI_arburst[1:0],S02_AXI_arlock[0:0],S02_AXI_arcache[3:0],S02_AXI_arprot[2:0],S02_AXI_arregion[3:0],S02_AXI_arqos[3:0],S02_AXI_arvalid[0:0],S02_AXI_arready[0:0],S02_AXI_rdata[127:0],S02_AXI_rresp[1:0],S02_AXI_rlast[0:0],S02_AXI_rvalid[0:0],S02_AXI_rready[0:0],S03_AXI_awaddr[63:0],S03_AXI_awlen[7:0],S03_AXI_awsize[2:0],S03_AXI_awburst[1:0],S03_AXI_awlock[0:0],S03_AXI_awcache[3:0],S03_AXI_awprot[2:0],S03_AXI_awregion[3:0],S03_AXI_awqos[3:0],S03_AXI_awvalid[0:0],S03_AXI_awready[0:0],S03_AXI_wdata[127:0],S03_AXI_wstrb[15:0],S03_AXI_wlast[0:0],S03_AXI_wvalid[0:0],S03_AXI_wready[0:0],S03_AXI_bresp[1:0],S03_AXI_bvalid[0:0],S03_AXI_bready[0:0],S03_AXI_araddr[63:0],S03_AXI_arlen[7:0],S03_AXI_arsize[2:0],S03_AXI_arburst[1:0],S03_AXI_arlock[0:0],S03_AXI_arcache[3:0],S03_AXI_arprot[2:0],S03_AXI_arregion[3:0],S03_AXI_arqos[3:0],S03_AXI_arvalid[0:0],S03_AXI_arready[0:0],S03_AXI_rdata[127:0],S03_AXI_rresp[1:0],S03_AXI_rlast[0:0],S03_AXI_rvalid[0:0],S03_AXI_rready[0:0],S04_AXI_awaddr[63:0],S04_AXI_awlen[7:0],S04_AXI_awsize[2:0],S04_AXI_awburst[1:0],S04_AXI_awlock[0:0],S04_AXI_awcache[3:0],S04_AXI_awprot[2:0],S04_AXI_awregion[3:0],S04_AXI_awqos[3:0],S04_AXI_awvalid[0:0],S04_AXI_awready[0:0],S04_AXI_wdata[127:0],S04_AXI_wstrb[15:0],S04_AXI_wlast[0:0],S04_AXI_wvalid[0:0],S04_AXI_wready[0:0],S04_AXI_bresp[1:0],S04_AXI_bvalid[0:0],S04_AXI_bready[0:0],S04_AXI_araddr[63:0],S04_AXI_arlen[7:0],S04_AXI_arsize[2:0],S04_AXI_arburst[1:0],S04_AXI_arlock[0:0],S04_AXI_arcache[3:0],S04_AXI_arprot[2:0],S04_AXI_arregion[3:0],S04_AXI_arqos[3:0],S04_AXI_arvalid[0:0],S04_AXI_arready[0:0],S04_AXI_rdata[127:0],S04_AXI_rresp[1:0],S04_AXI_rlast[0:0],S04_AXI_rvalid[0:0],S04_AXI_rready[0:0],S05_AXI_awaddr[63:0],S05_AXI_awlen[7:0],S05_AXI_awsize[2:0],S05_AXI_awburst[1:0],S05_AXI_awlock[0:0],S05_AXI_awcache[3:0],S05_AXI_awprot[2:0],S05_AXI_awregion[3:0],S05_AXI_awqos[3:0],S05_AXI_awvalid[0:0],S05_AXI_awready[0:0],S05_AXI_wdata[127:0],S05_AXI_wstrb[15:0],S05_AXI_wlast[0:0],S05_AXI_wvalid[0:0],S05_AXI_wready[0:0],S05_AXI_bresp[1:0],S05_AXI_bvalid[0:0],S05_AXI_bready[0:0],S05_AXI_araddr[63:0],S05_AXI_arlen[7:0],S05_AXI_arsize[2:0],S05_AXI_arburst[1:0],S05_AXI_arlock[0:0],S05_AXI_arcache[3:0],S05_AXI_arprot[2:0],S05_AXI_arregion[3:0],S05_AXI_arqos[3:0],S05_AXI_arvalid[0:0],S05_AXI_arready[0:0],S05_AXI_rdata[127:0],S05_AXI_rresp[1:0],S05_AXI_rlast[0:0],S05_AXI_rvalid[0:0],S05_AXI_rready[0:0],M00_AXI_awaddr[63:0],M00_AXI_awlen[7:0],M00_AXI_awsize[2:0],M00_AXI_awburst[1:0],M00_AXI_awlock[0:0],M00_AXI_awcache[3:0],M00_AXI_awprot[2:0],M00_AXI_awregion[3:0],M00_AXI_awqos[3:0],M00_AXI_awvalid[0:0],M00_AXI_awready[0:0],M00_AXI_wdata[127:0],M00_AXI_wstrb[15:0],M00_AXI_wlast[0:0],M00_AXI_wvalid[0:0],M00_AXI_wready[0:0],M00_AXI_bresp[1:0],M00_AXI_bvalid[0:0],M00_AXI_bready[0:0],M00_AXI_araddr[63:0],M00_AXI_arlen[7:0],M00_AXI_arsize[2:0],M00_AXI_arburst[1:0],M00_AXI_arlock[0:0],M00_AXI_arcache[3:0],M00_AXI_arprot[2:0],M00_AXI_arregion[3:0],M00_AXI_arqos[3:0],M00_AXI_arvalid[0:0],M00_AXI_arready[0:0],M00_AXI_rdata[127:0],M00_AXI_rresp[1:0],M00_AXI_rlast[0:0],M00_AXI_rvalid[0:0],M00_AXI_rready[0:0],M01_AXI_awaddr[63:0],M01_AXI_awlen[7:0],M01_AXI_awsize[2:0],M01_AXI_awburst[1:0],M01_AXI_awlock[0:0],M01_AXI_awcache[3:0],M01_AXI_awprot[2:0],M01_AXI_awregion[3:0],M01_AXI_awqos[3:0],M01_AXI_awvalid[0:0],M01_AXI_awready[0:0],M01_AXI_wdata[127:0],M01_AXI_wstrb[15:0],M01_AXI_wlast[0:0],M01_AXI_wvalid[0:0],M01_AXI_wready[0:0],M01_AXI_bresp[1:0],M01_AXI_bvalid[0:0],M01_AXI_bready[0:0],M01_AXI_araddr[63:0],M01_AXI_arlen[7:0],M01_AXI_arsize[2:0],M01_AXI_arburst[1:0],M01_AXI_arlock[0:0],M01_AXI_arcache[3:0],M01_AXI_arprot[2:0],M01_AXI_arregion[3:0],M01_AXI_arqos[3:0],M01_AXI_arvalid[0:0],M01_AXI_arready[0:0],M01_AXI_rdata[127:0],M01_AXI_rresp[1:0],M01_AXI_rlast[0:0],M01_AXI_rvalid[0:0],M01_AXI_rready[0:0],aclk0,aclk1,aclk2,aclk3,aclk4,aclk5,aclk6,aclk7,sys_clk0_clk_p[0:0],sys_clk0_clk_n[0:0],CH0_DDR4_0_dq[63:0],CH0_DDR4_0_dqs_t[7:0],CH0_DDR4_0_dqs_c[7:0],CH0_DDR4_0_adr[16:0],CH0_DDR4_0_ba[1:0],CH0_DDR4_0_bg[1:0],CH0_DDR4_0_act_n[0:0],CH0_DDR4_0_reset_n[0:0],CH0_DDR4_0_ck_t[0:0],CH0_DDR4_0_ck_c[0:0],CH0_DDR4_0_cke[0:0],CH0_DDR4_0_cs_n[0:0],CH0_DDR4_0_dm_n[7:0],CH0_DDR4_0_odt[0:0],S04_AXI_arid[15:0],S04_AXI_aruser[17:0],S04_AXI_awid[15:0],S04_AXI_awuser[17:0],S04_AXI_bid[15:0],S04_AXI_rid[15:0],S04_AXI_ruser[16:0],S04_AXI_wuser[16:0],S03_AXI_arid[15:0],S03_AXI_aruser[17:0],S03_AXI_awid[15:0],S03_AXI_awuser[17:0],S03_AXI_bid[15:0],S03_AXI_rid[15:0],S03_AXI_ruser[16:0],S03_AXI_wuser[16:0],S02_AXI_arid[15:0],S02_AXI_aruser[17:0],S02_AXI_awid[15:0],S02_AXI_awuser[17:0],S02_AXI_bid[15:0],S02_AXI_rid[15:0],S02_AXI_ruser[16:0],S02_AXI_wuser[16:0],S00_AXI_arid[15:0],S00_AXI_aruser[17:0],S00_AXI_awid[15:0],S00_AXI_awuser[17:0],S00_AXI_bid[15:0],S00_AXI_rid[15:0],S00_AXI_ruser[16:0],S00_AXI_wuser[16:0],S05_AXI_arid[15:0],S05_AXI_aruser[17:0],S05_AXI_awid[15:0],S05_AXI_awuser[17:0],S05_AXI_bid[15:0],S05_AXI_buser[15:0],S05_AXI_rid[15:0],S05_AXI_ruser[16:0],S05_AXI_wuser[16:0],S01_AXI_arid[15:0],S01_AXI_aruser[17:0],S01_AXI_awid[15:0],S01_AXI_awuser[17:0],S01_AXI_bid[15:0],S01_AXI_rid[15:0],S01_AXI_ruser[16:0],S01_AXI_wuser[16:0],M01_AXI_arid[1:0],M01_AXI_aruser[17:0],M01_AXI_awid[1:0],M01_AXI_awuser[17:0],M01_AXI_bid[1:0],M01_AXI_rid[1:0],M00_AXI_arid[1:0],M00_AXI_aruser[17:0],M00_AXI_awid[1:0],M00_AXI_awuser[17:0],M00_AXI_bid[1:0],M00_AXI_rid[1:0],M00_AXI_ruser[16:0],M00_AXI_wuser[16:0]";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of S00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
  attribute X_INTERFACE_MODE : string;
  attribute X_INTERFACE_MODE of S00_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of S00_AXI_awaddr : signal is "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi0_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, R_TRAFFIC_CLASS BEST_EFFORT, W_TRAFFIC_CLASS BEST_EFFORT, R_LATENCY 300, R_RATE_LIMITER 10, W_RATE_LIMITER 10, R_MAX_BURST_LENGTH 256, W_MAX_BURST_LENGTH 256, REGION 0, CONNECTIONS MC_0 {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}, DEST_IDS M01_AXI:0x0, WRITE_BUFFER_SIZE 80, MY_CATEGORY noc, CATEGORY ps_cci";
  attribute X_INTERFACE_INFO of S00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN";
  attribute X_INTERFACE_INFO of S00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST";
  attribute X_INTERFACE_INFO of S00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
  attribute X_INTERFACE_INFO of S00_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREGION";
  attribute X_INTERFACE_INFO of S00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS";
  attribute X_INTERFACE_INFO of S00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
  attribute X_INTERFACE_INFO of S00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
  attribute X_INTERFACE_INFO of S00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
  attribute X_INTERFACE_INFO of S00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
  attribute X_INTERFACE_INFO of S00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WLAST";
  attribute X_INTERFACE_INFO of S00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
  attribute X_INTERFACE_INFO of S00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
  attribute X_INTERFACE_INFO of S00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
  attribute X_INTERFACE_INFO of S00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
  attribute X_INTERFACE_INFO of S00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
  attribute X_INTERFACE_INFO of S00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
  attribute X_INTERFACE_INFO of S00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN";
  attribute X_INTERFACE_INFO of S00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST";
  attribute X_INTERFACE_INFO of S00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
  attribute X_INTERFACE_INFO of S00_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREGION";
  attribute X_INTERFACE_INFO of S00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS";
  attribute X_INTERFACE_INFO of S00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
  attribute X_INTERFACE_INFO of S00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
  attribute X_INTERFACE_INFO of S00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
  attribute X_INTERFACE_INFO of S00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
  attribute X_INTERFACE_INFO of S00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RLAST";
  attribute X_INTERFACE_INFO of S00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
  attribute X_INTERFACE_INFO of S00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
  attribute X_INTERFACE_INFO of S01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWADDR";
  attribute X_INTERFACE_MODE of S01_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S01_AXI_awaddr : signal is "XIL_INTERFACENAME S01_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi1_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, R_TRAFFIC_CLASS BEST_EFFORT, W_TRAFFIC_CLASS BEST_EFFORT, R_LATENCY 300, R_RATE_LIMITER 10, W_RATE_LIMITER 10, R_MAX_BURST_LENGTH 256, W_MAX_BURST_LENGTH 256, REGION 0, CONNECTIONS MC_0 {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}, DEST_IDS M01_AXI:0x0, WRITE_BUFFER_SIZE 80, MY_CATEGORY noc, CATEGORY ps_cci";
  attribute X_INTERFACE_INFO of S01_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLEN";
  attribute X_INTERFACE_INFO of S01_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S01_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWBURST";
  attribute X_INTERFACE_INFO of S01_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S01_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWPROT";
  attribute X_INTERFACE_INFO of S01_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREGION";
  attribute X_INTERFACE_INFO of S01_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWQOS";
  attribute X_INTERFACE_INFO of S01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWVALID";
  attribute X_INTERFACE_INFO of S01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWREADY";
  attribute X_INTERFACE_INFO of S01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WDATA";
  attribute X_INTERFACE_INFO of S01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WSTRB";
  attribute X_INTERFACE_INFO of S01_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WLAST";
  attribute X_INTERFACE_INFO of S01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WVALID";
  attribute X_INTERFACE_INFO of S01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WREADY";
  attribute X_INTERFACE_INFO of S01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BRESP";
  attribute X_INTERFACE_INFO of S01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BVALID";
  attribute X_INTERFACE_INFO of S01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BREADY";
  attribute X_INTERFACE_INFO of S01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARADDR";
  attribute X_INTERFACE_INFO of S01_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLEN";
  attribute X_INTERFACE_INFO of S01_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S01_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARBURST";
  attribute X_INTERFACE_INFO of S01_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S01_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARPROT";
  attribute X_INTERFACE_INFO of S01_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREGION";
  attribute X_INTERFACE_INFO of S01_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARQOS";
  attribute X_INTERFACE_INFO of S01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARVALID";
  attribute X_INTERFACE_INFO of S01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARREADY";
  attribute X_INTERFACE_INFO of S01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RDATA";
  attribute X_INTERFACE_INFO of S01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RRESP";
  attribute X_INTERFACE_INFO of S01_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RLAST";
  attribute X_INTERFACE_INFO of S01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RVALID";
  attribute X_INTERFACE_INFO of S01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RREADY";
  attribute X_INTERFACE_INFO of S02_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWADDR";
  attribute X_INTERFACE_MODE of S02_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S02_AXI_awaddr : signal is "XIL_INTERFACENAME S02_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi2_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, R_TRAFFIC_CLASS BEST_EFFORT, W_TRAFFIC_CLASS BEST_EFFORT, R_LATENCY 300, R_RATE_LIMITER 10, W_RATE_LIMITER 10, R_MAX_BURST_LENGTH 256, W_MAX_BURST_LENGTH 256, REGION 0, CONNECTIONS MC_1 {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}, DEST_IDS M01_AXI:0x0, WRITE_BUFFER_SIZE 80, MY_CATEGORY noc, CATEGORY ps_cci";
  attribute X_INTERFACE_INFO of S02_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWLEN";
  attribute X_INTERFACE_INFO of S02_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S02_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWBURST";
  attribute X_INTERFACE_INFO of S02_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S02_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S02_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWPROT";
  attribute X_INTERFACE_INFO of S02_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWREGION";
  attribute X_INTERFACE_INFO of S02_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWQOS";
  attribute X_INTERFACE_INFO of S02_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWVALID";
  attribute X_INTERFACE_INFO of S02_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWREADY";
  attribute X_INTERFACE_INFO of S02_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WDATA";
  attribute X_INTERFACE_INFO of S02_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WSTRB";
  attribute X_INTERFACE_INFO of S02_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WLAST";
  attribute X_INTERFACE_INFO of S02_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WVALID";
  attribute X_INTERFACE_INFO of S02_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WREADY";
  attribute X_INTERFACE_INFO of S02_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BRESP";
  attribute X_INTERFACE_INFO of S02_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BVALID";
  attribute X_INTERFACE_INFO of S02_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BREADY";
  attribute X_INTERFACE_INFO of S02_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARADDR";
  attribute X_INTERFACE_INFO of S02_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARLEN";
  attribute X_INTERFACE_INFO of S02_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S02_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARBURST";
  attribute X_INTERFACE_INFO of S02_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S02_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S02_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARPROT";
  attribute X_INTERFACE_INFO of S02_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARREGION";
  attribute X_INTERFACE_INFO of S02_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARQOS";
  attribute X_INTERFACE_INFO of S02_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARVALID";
  attribute X_INTERFACE_INFO of S02_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARREADY";
  attribute X_INTERFACE_INFO of S02_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RDATA";
  attribute X_INTERFACE_INFO of S02_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RRESP";
  attribute X_INTERFACE_INFO of S02_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RLAST";
  attribute X_INTERFACE_INFO of S02_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RVALID";
  attribute X_INTERFACE_INFO of S02_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RREADY";
  attribute X_INTERFACE_INFO of S03_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWADDR";
  attribute X_INTERFACE_MODE of S03_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S03_AXI_awaddr : signal is "XIL_INTERFACENAME S03_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi3_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, R_TRAFFIC_CLASS BEST_EFFORT, W_TRAFFIC_CLASS BEST_EFFORT, R_LATENCY 300, R_RATE_LIMITER 10, W_RATE_LIMITER 10, R_MAX_BURST_LENGTH 256, W_MAX_BURST_LENGTH 256, REGION 0, CONNECTIONS MC_2 {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}, DEST_IDS M01_AXI:0x0, WRITE_BUFFER_SIZE 80, MY_CATEGORY noc, CATEGORY ps_cci";
  attribute X_INTERFACE_INFO of S03_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWLEN";
  attribute X_INTERFACE_INFO of S03_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S03_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWBURST";
  attribute X_INTERFACE_INFO of S03_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S03_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S03_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWPROT";
  attribute X_INTERFACE_INFO of S03_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWREGION";
  attribute X_INTERFACE_INFO of S03_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWQOS";
  attribute X_INTERFACE_INFO of S03_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWVALID";
  attribute X_INTERFACE_INFO of S03_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWREADY";
  attribute X_INTERFACE_INFO of S03_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WDATA";
  attribute X_INTERFACE_INFO of S03_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WSTRB";
  attribute X_INTERFACE_INFO of S03_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WLAST";
  attribute X_INTERFACE_INFO of S03_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WVALID";
  attribute X_INTERFACE_INFO of S03_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WREADY";
  attribute X_INTERFACE_INFO of S03_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BRESP";
  attribute X_INTERFACE_INFO of S03_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BVALID";
  attribute X_INTERFACE_INFO of S03_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BREADY";
  attribute X_INTERFACE_INFO of S03_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARADDR";
  attribute X_INTERFACE_INFO of S03_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARLEN";
  attribute X_INTERFACE_INFO of S03_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S03_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARBURST";
  attribute X_INTERFACE_INFO of S03_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S03_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S03_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARPROT";
  attribute X_INTERFACE_INFO of S03_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARREGION";
  attribute X_INTERFACE_INFO of S03_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARQOS";
  attribute X_INTERFACE_INFO of S03_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARVALID";
  attribute X_INTERFACE_INFO of S03_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARREADY";
  attribute X_INTERFACE_INFO of S03_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RDATA";
  attribute X_INTERFACE_INFO of S03_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RRESP";
  attribute X_INTERFACE_INFO of S03_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RLAST";
  attribute X_INTERFACE_INFO of S03_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RVALID";
  attribute X_INTERFACE_INFO of S03_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RREADY";
  attribute X_INTERFACE_INFO of S04_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWADDR";
  attribute X_INTERFACE_MODE of S04_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S04_AXI_awaddr : signal is "XIL_INTERFACENAME S04_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 599999451, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_lpd_axi_noc_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, R_TRAFFIC_CLASS BEST_EFFORT, W_TRAFFIC_CLASS BEST_EFFORT, R_LATENCY 300, R_RATE_LIMITER 10, W_RATE_LIMITER 10, R_MAX_BURST_LENGTH 256, W_MAX_BURST_LENGTH 256, REGION 0, CONNECTIONS MC_3 {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}, DEST_IDS M01_AXI:0x0, WRITE_BUFFER_SIZE 80, MY_CATEGORY noc, CATEGORY ps_rpu";
  attribute X_INTERFACE_INFO of S04_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWLEN";
  attribute X_INTERFACE_INFO of S04_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S04_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWBURST";
  attribute X_INTERFACE_INFO of S04_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S04_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S04_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWPROT";
  attribute X_INTERFACE_INFO of S04_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWREGION";
  attribute X_INTERFACE_INFO of S04_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWQOS";
  attribute X_INTERFACE_INFO of S04_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWVALID";
  attribute X_INTERFACE_INFO of S04_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWREADY";
  attribute X_INTERFACE_INFO of S04_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WDATA";
  attribute X_INTERFACE_INFO of S04_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WSTRB";
  attribute X_INTERFACE_INFO of S04_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WLAST";
  attribute X_INTERFACE_INFO of S04_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WVALID";
  attribute X_INTERFACE_INFO of S04_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WREADY";
  attribute X_INTERFACE_INFO of S04_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BRESP";
  attribute X_INTERFACE_INFO of S04_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BVALID";
  attribute X_INTERFACE_INFO of S04_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BREADY";
  attribute X_INTERFACE_INFO of S04_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARADDR";
  attribute X_INTERFACE_INFO of S04_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARLEN";
  attribute X_INTERFACE_INFO of S04_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S04_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARBURST";
  attribute X_INTERFACE_INFO of S04_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S04_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S04_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARPROT";
  attribute X_INTERFACE_INFO of S04_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARREGION";
  attribute X_INTERFACE_INFO of S04_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARQOS";
  attribute X_INTERFACE_INFO of S04_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARVALID";
  attribute X_INTERFACE_INFO of S04_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARREADY";
  attribute X_INTERFACE_INFO of S04_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RDATA";
  attribute X_INTERFACE_INFO of S04_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RRESP";
  attribute X_INTERFACE_INFO of S04_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RLAST";
  attribute X_INTERFACE_INFO of S04_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RVALID";
  attribute X_INTERFACE_INFO of S04_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RREADY";
  attribute X_INTERFACE_INFO of S05_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWADDR";
  attribute X_INTERFACE_MODE of S05_AXI_awaddr : signal is "slave";
  attribute X_INTERFACE_PARAMETER of S05_AXI_awaddr : signal is "XIL_INTERFACENAME S05_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 400000000, ID_WIDTH 16, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 17, RUSER_WIDTH 17, BUSER_WIDTH 16, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 64, NUM_WRITE_OUTSTANDING 64, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pmc_axi_noc_axi0_clk, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, R_TRAFFIC_CLASS BEST_EFFORT, W_TRAFFIC_CLASS BEST_EFFORT, R_LATENCY 300, R_RATE_LIMITER 10, W_RATE_LIMITER 10, R_MAX_BURST_LENGTH 256, W_MAX_BURST_LENGTH 256, REGION 0, CONNECTIONS M01_AXI {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}} MC_3 {read_bw {500} write_bw {500} read_avg_burst {4} write_avg_burst {4}}, DEST_IDS M01_AXI:0x0, WRITE_BUFFER_SIZE 80, MY_CATEGORY noc, CATEGORY ps_pmc";
  attribute X_INTERFACE_INFO of S05_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWLEN";
  attribute X_INTERFACE_INFO of S05_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWSIZE";
  attribute X_INTERFACE_INFO of S05_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWBURST";
  attribute X_INTERFACE_INFO of S05_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWLOCK";
  attribute X_INTERFACE_INFO of S05_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWCACHE";
  attribute X_INTERFACE_INFO of S05_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWPROT";
  attribute X_INTERFACE_INFO of S05_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWREGION";
  attribute X_INTERFACE_INFO of S05_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWQOS";
  attribute X_INTERFACE_INFO of S05_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWVALID";
  attribute X_INTERFACE_INFO of S05_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWREADY";
  attribute X_INTERFACE_INFO of S05_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WDATA";
  attribute X_INTERFACE_INFO of S05_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WSTRB";
  attribute X_INTERFACE_INFO of S05_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WLAST";
  attribute X_INTERFACE_INFO of S05_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WVALID";
  attribute X_INTERFACE_INFO of S05_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WREADY";
  attribute X_INTERFACE_INFO of S05_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BRESP";
  attribute X_INTERFACE_INFO of S05_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BVALID";
  attribute X_INTERFACE_INFO of S05_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BREADY";
  attribute X_INTERFACE_INFO of S05_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARADDR";
  attribute X_INTERFACE_INFO of S05_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARLEN";
  attribute X_INTERFACE_INFO of S05_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARSIZE";
  attribute X_INTERFACE_INFO of S05_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARBURST";
  attribute X_INTERFACE_INFO of S05_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARLOCK";
  attribute X_INTERFACE_INFO of S05_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARCACHE";
  attribute X_INTERFACE_INFO of S05_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARPROT";
  attribute X_INTERFACE_INFO of S05_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARREGION";
  attribute X_INTERFACE_INFO of S05_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARQOS";
  attribute X_INTERFACE_INFO of S05_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARVALID";
  attribute X_INTERFACE_INFO of S05_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARREADY";
  attribute X_INTERFACE_INFO of S05_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RDATA";
  attribute X_INTERFACE_INFO of S05_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RRESP";
  attribute X_INTERFACE_INFO of S05_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RLAST";
  attribute X_INTERFACE_INFO of S05_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RVALID";
  attribute X_INTERFACE_INFO of S05_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RREADY";
  attribute X_INTERFACE_INFO of M00_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR";
  attribute X_INTERFACE_MODE of M00_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M00_AXI_awaddr : signal is "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 799999268, ID_WIDTH 2, ADDR_WIDTH 64, AWUSER_WIDTH 16, ARUSER_WIDTH 16, WUSER_WIDTH 16, RUSER_WIDTH 16, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 32, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_noc_fpd_axi_axi0_clk, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, WRITE_BUFFER_SIZE 80, NOC_ID -1, MY_CATEGORY noc, CATEGORY ps_nci_phy";
  attribute X_INTERFACE_INFO of M00_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN";
  attribute X_INTERFACE_INFO of M00_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE";
  attribute X_INTERFACE_INFO of M00_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST";
  attribute X_INTERFACE_INFO of M00_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK";
  attribute X_INTERFACE_INFO of M00_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE";
  attribute X_INTERFACE_INFO of M00_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT";
  attribute X_INTERFACE_INFO of M00_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION";
  attribute X_INTERFACE_INFO of M00_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS";
  attribute X_INTERFACE_INFO of M00_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID";
  attribute X_INTERFACE_INFO of M00_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY";
  attribute X_INTERFACE_INFO of M00_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WDATA";
  attribute X_INTERFACE_INFO of M00_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB";
  attribute X_INTERFACE_INFO of M00_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WLAST";
  attribute X_INTERFACE_INFO of M00_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WVALID";
  attribute X_INTERFACE_INFO of M00_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WREADY";
  attribute X_INTERFACE_INFO of M00_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BRESP";
  attribute X_INTERFACE_INFO of M00_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BVALID";
  attribute X_INTERFACE_INFO of M00_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BREADY";
  attribute X_INTERFACE_INFO of M00_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR";
  attribute X_INTERFACE_INFO of M00_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN";
  attribute X_INTERFACE_INFO of M00_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE";
  attribute X_INTERFACE_INFO of M00_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST";
  attribute X_INTERFACE_INFO of M00_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK";
  attribute X_INTERFACE_INFO of M00_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE";
  attribute X_INTERFACE_INFO of M00_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT";
  attribute X_INTERFACE_INFO of M00_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION";
  attribute X_INTERFACE_INFO of M00_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS";
  attribute X_INTERFACE_INFO of M00_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID";
  attribute X_INTERFACE_INFO of M00_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY";
  attribute X_INTERFACE_INFO of M00_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RDATA";
  attribute X_INTERFACE_INFO of M00_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RRESP";
  attribute X_INTERFACE_INFO of M00_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RLAST";
  attribute X_INTERFACE_INFO of M00_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RVALID";
  attribute X_INTERFACE_INFO of M00_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RREADY";
  attribute X_INTERFACE_INFO of M01_AXI_awaddr : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWADDR";
  attribute X_INTERFACE_MODE of M01_AXI_awaddr : signal is "master";
  attribute X_INTERFACE_PARAMETER of M01_AXI_awaddr : signal is "XIL_INTERFACENAME M01_AXI, DATA_WIDTH 128, PROTOCOL AXI4, FREQ_HZ 99999908, ID_WIDTH 2, ADDR_WIDTH 64, AWUSER_WIDTH 18, ARUSER_WIDTH 18, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 32, NUM_WRITE_OUTSTANDING 32, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pl0_ref_clk, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0, WRITE_BUFFER_SIZE 80, NOC_ID -1, APERTURES {0x201_0000_0000 1G}, MY_CATEGORY noc, CATEGORY pl";
  attribute X_INTERFACE_INFO of M01_AXI_awlen : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWLEN";
  attribute X_INTERFACE_INFO of M01_AXI_awsize : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE";
  attribute X_INTERFACE_INFO of M01_AXI_awburst : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWBURST";
  attribute X_INTERFACE_INFO of M01_AXI_awlock : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK";
  attribute X_INTERFACE_INFO of M01_AXI_awcache : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE";
  attribute X_INTERFACE_INFO of M01_AXI_awprot : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWPROT";
  attribute X_INTERFACE_INFO of M01_AXI_awregion : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWREGION";
  attribute X_INTERFACE_INFO of M01_AXI_awqos : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWQOS";
  attribute X_INTERFACE_INFO of M01_AXI_awvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWVALID";
  attribute X_INTERFACE_INFO of M01_AXI_awready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWREADY";
  attribute X_INTERFACE_INFO of M01_AXI_wdata : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WDATA";
  attribute X_INTERFACE_INFO of M01_AXI_wstrb : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WSTRB";
  attribute X_INTERFACE_INFO of M01_AXI_wlast : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WLAST";
  attribute X_INTERFACE_INFO of M01_AXI_wvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WVALID";
  attribute X_INTERFACE_INFO of M01_AXI_wready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI WREADY";
  attribute X_INTERFACE_INFO of M01_AXI_bresp : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BRESP";
  attribute X_INTERFACE_INFO of M01_AXI_bvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BVALID";
  attribute X_INTERFACE_INFO of M01_AXI_bready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BREADY";
  attribute X_INTERFACE_INFO of M01_AXI_araddr : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARADDR";
  attribute X_INTERFACE_INFO of M01_AXI_arlen : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARLEN";
  attribute X_INTERFACE_INFO of M01_AXI_arsize : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE";
  attribute X_INTERFACE_INFO of M01_AXI_arburst : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARBURST";
  attribute X_INTERFACE_INFO of M01_AXI_arlock : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK";
  attribute X_INTERFACE_INFO of M01_AXI_arcache : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE";
  attribute X_INTERFACE_INFO of M01_AXI_arprot : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARPROT";
  attribute X_INTERFACE_INFO of M01_AXI_arregion : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARREGION";
  attribute X_INTERFACE_INFO of M01_AXI_arqos : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARQOS";
  attribute X_INTERFACE_INFO of M01_AXI_arvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARVALID";
  attribute X_INTERFACE_INFO of M01_AXI_arready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARREADY";
  attribute X_INTERFACE_INFO of M01_AXI_rdata : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RDATA";
  attribute X_INTERFACE_INFO of M01_AXI_rresp : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RRESP";
  attribute X_INTERFACE_INFO of M01_AXI_rlast : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RLAST";
  attribute X_INTERFACE_INFO of M01_AXI_rvalid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RVALID";
  attribute X_INTERFACE_INFO of M01_AXI_rready : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RREADY";
  attribute X_INTERFACE_INFO of aclk0 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk0 CLK";
  attribute X_INTERFACE_MODE of aclk0 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk0 : signal is "XIL_INTERFACENAME CLK.aclk0, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi0_clk, ASSOCIATED_BUSIF S00_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk1 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk1 CLK";
  attribute X_INTERFACE_MODE of aclk1 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk1 : signal is "XIL_INTERFACENAME CLK.aclk1, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi1_clk, ASSOCIATED_BUSIF S01_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk2 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk2 CLK";
  attribute X_INTERFACE_MODE of aclk2 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk2 : signal is "XIL_INTERFACENAME CLK.aclk2, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi2_clk, ASSOCIATED_BUSIF S02_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk3 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk3 CLK";
  attribute X_INTERFACE_MODE of aclk3 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk3 : signal is "XIL_INTERFACENAME CLK.aclk3, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_fpd_cci_noc_axi3_clk, ASSOCIATED_BUSIF S03_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk4 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk4 CLK";
  attribute X_INTERFACE_MODE of aclk4 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk4 : signal is "XIL_INTERFACENAME CLK.aclk4, FREQ_HZ 599999451, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_lpd_axi_noc_clk, ASSOCIATED_BUSIF S04_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk5 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk5 CLK";
  attribute X_INTERFACE_MODE of aclk5 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk5 : signal is "XIL_INTERFACENAME CLK.aclk5, FREQ_HZ 400000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pmc_axi_noc_axi0_clk, ASSOCIATED_BUSIF S05_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk6 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk6 CLK";
  attribute X_INTERFACE_MODE of aclk6 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk6 : signal is "XIL_INTERFACENAME CLK.aclk6, FREQ_HZ 799999268, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_noc_fpd_axi_axi0_clk, ASSOCIATED_BUSIF M00_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of aclk7 : signal is "xilinx.com:signal:clock:1.0 CLK.aclk7 CLK";
  attribute X_INTERFACE_MODE of aclk7 : signal is "slave";
  attribute X_INTERFACE_PARAMETER of aclk7 : signal is "XIL_INTERFACENAME CLK.aclk7, FREQ_HZ 99999908, FREQ_TOLERANCE_HZ 0, PHASE 0.0, CLK_DOMAIN bd_70da_pspmc_0_0_pl0_ref_clk, ASSOCIATED_BUSIF M01_AXI, INSERT_VIP 0";
  attribute X_INTERFACE_INFO of sys_clk0_clk_p : signal is "xilinx.com:interface:diff_clock:1.0 sys_clk0 CLK_P";
  attribute X_INTERFACE_MODE of sys_clk0_clk_p : signal is "slave";
  attribute X_INTERFACE_PARAMETER of sys_clk0_clk_p : signal is "XIL_INTERFACENAME sys_clk0, CAN_DEBUG false, FREQ_HZ 200000000, BOARD.ASSOCIATED_PARAM sys_clk0_BOARD_INTERFACE";
  attribute X_INTERFACE_INFO of sys_clk0_clk_n : signal is "xilinx.com:interface:diff_clock:1.0 sys_clk0 CLK_N";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_dq : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 DQ";
  attribute X_INTERFACE_MODE of CH0_DDR4_0_dq : signal is "master";
  attribute X_INTERFACE_PARAMETER of CH0_DDR4_0_dq : signal is "XIL_INTERFACENAME CH0_DDR4_0, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, WRITE_BUFFER_SIZE 80, NOC_ID -1, MY_CATEGORY pl, BOARD.ASSOCIATED_PARAM CH0_DDR4_0_BOARD_INTERFACE";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_dqs_t : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 DQS_T";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_dqs_c : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 DQS_C";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_adr : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 ADR";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_ba : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 BA";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_bg : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 BG";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_act_n : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 ACT_N";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_reset_n : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 RESET_N";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_ck_t : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 CK_T";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_ck_c : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 CK_C";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_cke : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 CKE";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_cs_n : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 CS_N";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_dm_n : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 DM_N";
  attribute X_INTERFACE_INFO of CH0_DDR4_0_odt : signal is "xilinx.com:interface:ddr4:1.0 CH0_DDR4_0 ODT";
  attribute X_INTERFACE_INFO of S04_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARID";
  attribute X_INTERFACE_INFO of S04_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 S04_AXI ARUSER";
  attribute X_INTERFACE_INFO of S04_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWID";
  attribute X_INTERFACE_INFO of S04_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 S04_AXI AWUSER";
  attribute X_INTERFACE_INFO of S04_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI BID";
  attribute X_INTERFACE_INFO of S04_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RID";
  attribute X_INTERFACE_INFO of S04_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 S04_AXI RUSER";
  attribute X_INTERFACE_INFO of S04_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 S04_AXI WUSER";
  attribute X_INTERFACE_INFO of S03_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARID";
  attribute X_INTERFACE_INFO of S03_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 S03_AXI ARUSER";
  attribute X_INTERFACE_INFO of S03_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWID";
  attribute X_INTERFACE_INFO of S03_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 S03_AXI AWUSER";
  attribute X_INTERFACE_INFO of S03_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI BID";
  attribute X_INTERFACE_INFO of S03_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RID";
  attribute X_INTERFACE_INFO of S03_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 S03_AXI RUSER";
  attribute X_INTERFACE_INFO of S03_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 S03_AXI WUSER";
  attribute X_INTERFACE_INFO of S02_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARID";
  attribute X_INTERFACE_INFO of S02_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 S02_AXI ARUSER";
  attribute X_INTERFACE_INFO of S02_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWID";
  attribute X_INTERFACE_INFO of S02_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 S02_AXI AWUSER";
  attribute X_INTERFACE_INFO of S02_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI BID";
  attribute X_INTERFACE_INFO of S02_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RID";
  attribute X_INTERFACE_INFO of S02_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 S02_AXI RUSER";
  attribute X_INTERFACE_INFO of S02_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 S02_AXI WUSER";
  attribute X_INTERFACE_INFO of S00_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARID";
  attribute X_INTERFACE_INFO of S00_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARUSER";
  attribute X_INTERFACE_INFO of S00_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWID";
  attribute X_INTERFACE_INFO of S00_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWUSER";
  attribute X_INTERFACE_INFO of S00_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BID";
  attribute X_INTERFACE_INFO of S00_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RID";
  attribute X_INTERFACE_INFO of S00_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RUSER";
  attribute X_INTERFACE_INFO of S00_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WUSER";
  attribute X_INTERFACE_INFO of S05_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARID";
  attribute X_INTERFACE_INFO of S05_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 S05_AXI ARUSER";
  attribute X_INTERFACE_INFO of S05_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWID";
  attribute X_INTERFACE_INFO of S05_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 S05_AXI AWUSER";
  attribute X_INTERFACE_INFO of S05_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BID";
  attribute X_INTERFACE_INFO of S05_AXI_buser : signal is "xilinx.com:interface:aximm:1.0 S05_AXI BUSER";
  attribute X_INTERFACE_INFO of S05_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RID";
  attribute X_INTERFACE_INFO of S05_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 S05_AXI RUSER";
  attribute X_INTERFACE_INFO of S05_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 S05_AXI WUSER";
  attribute X_INTERFACE_INFO of S01_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARID";
  attribute X_INTERFACE_INFO of S01_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 S01_AXI ARUSER";
  attribute X_INTERFACE_INFO of S01_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWID";
  attribute X_INTERFACE_INFO of S01_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 S01_AXI AWUSER";
  attribute X_INTERFACE_INFO of S01_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI BID";
  attribute X_INTERFACE_INFO of S01_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RID";
  attribute X_INTERFACE_INFO of S01_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 S01_AXI RUSER";
  attribute X_INTERFACE_INFO of S01_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 S01_AXI WUSER";
  attribute X_INTERFACE_INFO of M01_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARID";
  attribute X_INTERFACE_INFO of M01_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 M01_AXI ARUSER";
  attribute X_INTERFACE_INFO of M01_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWID";
  attribute X_INTERFACE_INFO of M01_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 M01_AXI AWUSER";
  attribute X_INTERFACE_INFO of M01_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI BID";
  attribute X_INTERFACE_INFO of M01_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 M01_AXI RID";
  attribute X_INTERFACE_INFO of M00_AXI_arid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARID";
  attribute X_INTERFACE_INFO of M00_AXI_aruser : signal is "xilinx.com:interface:aximm:1.0 M00_AXI ARUSER";
  attribute X_INTERFACE_INFO of M00_AXI_awid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWID";
  attribute X_INTERFACE_INFO of M00_AXI_awuser : signal is "xilinx.com:interface:aximm:1.0 M00_AXI AWUSER";
  attribute X_INTERFACE_INFO of M00_AXI_bid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI BID";
  attribute X_INTERFACE_INFO of M00_AXI_rid : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RID";
  attribute X_INTERFACE_INFO of M00_AXI_ruser : signal is "xilinx.com:interface:aximm:1.0 M00_AXI RUSER";
  attribute X_INTERFACE_INFO of M00_AXI_wuser : signal is "xilinx.com:interface:aximm:1.0 M00_AXI WUSER";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of stub : architecture is "bd_8be5,Vivado 2025.1";
begin
end;
